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1/15 april 2000 m27w202 2 mbit (128kb x16) low voltage uv eprom and otp eprom n 2.7v to 3.6v supply voltage in read operation n access time: C80ns at v cc = 3.0v to 3.6v C 100ns at v cc = 2.7v to 3.6v n low power consumption: C active current 20ma at 5mhz C standby current 15a n pin compatible with m27c202 n programming time: 100s/word n high reliability cmos technology C 2,000v esd protection C 200ma latchup protection immunity n electronic signature C manufacturer code: 0020h C device code: 001ch description the m27w202 is a low voltage 2 mbit eprom of- fered in the two range uv (ultra violet erase) and otp (one time programmable). it is ideally suited for microprocessor systems requiring large data or program storage and is organised as 131,072 by 16 bits. the m27w202 operates in the read mode with a supply voltage as low as 2.7v at C40 to 85c tem- perature range. the decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery re- charges. the fdip40w (window ceramic frit-seal package) has a transparent lid which allows the user to ex- pose the chip to ultraviolet light to erase the bit pat- tern. a new pattern can then be written to the device by following the programming procedure. for application where the content is programmed only one time and erasure is not required, the m27w201 is offered in pdip40, plcc44 and tsop40 (10 x 14 mm) packages. figure 1. logic diagram ai02730 17 a0-a16 p q0-q15 v pp v cc m27w202 g e v ss 16 1 40 1 40 pdip40 (b) plcc44 (k) tsop40 (n) 10 x 14 mm fdip40w (f)
m27w202 2/15 figure 2b. lcc connections ai02732 a14 a11 a7 a3 23 q6 q5 q4 q3 q2 nc a2 q12 q8 v ss nc q11 q10 12 a15 a9 1 q15 v ss a12 q13 a5 44 nc a16 m27w202 q14 a13 a4 nc a6 34 q1 q9 a10 a8 q7 q0 g a0 a1 v pp e p v cc figure 2a. dip connections q6 q5 q4 q11 q8 v ss q7 q10 q9 a12 a8 a11 a10 a6 a13 a9 v ss a7 a2 q1 q0 a0 g a1 a5 a16 p e q12 v pp v cc q15 ai02731 m27w202 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 q3 q2 q14 q13 a4 a3 40 39 38 37 36 35 34 33 a14 a15 figure 2c. tsop connections dq6 dq3 dq2 dq13 dq8 dq7 dq10 dq9 a14 a8 a11 a10 a4 a15 a9 g a7 a2 dq1 dq0 a0 a1 a3 a16 p e dq14 v pp v cc dq15 ai02733 m27w202 (normal) 10 1 11 20 21 30 31 40 v ss a12 a6 a13 a5 dq12 dq4 dq11 dq5 v ss table 1. signal names a0-a16 address inputs q0-q15 data outputs e chip enable g output enable p program v pp program supply v cc supply voltage v ss ground nc not connected internally
3/15 m27w202 table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition s above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum dc voltage on input or output is C0.5v with possible undershoot to C2.0v for a period less than 20ns. maximum dc voltage on output is v cc +0.5v with possible overshoot to v cc +2v for a period less than 20ns. 3. depends on range. table 3. operating modes note: x = v ih or v il , v id = 12v 0.5v. table 4. electronic signature note: outputs q15-q8 are set to '0'. symbol parameter value unit t a ambient operating temperature (3) C40 to 125 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltage (except a9) C2 to 7 v v cc supply voltage C2 to 7 v v a9 (2) a9 voltage C2 to 13.5 v v pp program supply voltage C2 to 14 v mode e g p a9 v pp q15-q0 read v il v il v ih x v cc or v ss data output output disable v il v ih xx v cc or v ss hi-z program v il x v il pulse x v pp data input verify v il v il v ih x v pp data output program inhibit v ih xxx v pp hi-z standby v ih xxx v cc or v ss hi-z electronic signature v il v il v ih v id v cc codes identifier a0 q7 q6 q5 q4 q3 q2 q1 q0 hex data manufacturers code v il 00100000 20h device code v ih 00011100 1ch
m27w202 4/15 table 5. ac measurement conditions high speed standard input rise and fall times 10ns 20ns input pulse voltages 0 to 3v 0.4v to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v figure 3. ac testing input output waveform ai01822 3v high speed 0v 1.5v 2.4v standard 0.4v 2.0v 0.8v figure 4. ac testing load circuit ai01823b 1.3v out c l c l = 30pf for high speed c l = 100pf for standard c l includes jig capacitance 3.3k w 1n914 device under test table 6. capacitance (1) (t a = 25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf device operation the operating modes of the m27w202 are listed in the operating modes table. a single power supply is required in the read mode. all inputs are ttl levels except for v pp and 12v on a9 for electronic signature. read mode the m27w202 has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (e ) is the power control and should be used for device selection. output enable (g ) is the output control and should be used to gate data to the output pins, indepen- dent of device selection. assuming that the ad- dresses are stable, the address access time (t avqv ) is equal to the delay from e to output (t elqv ). data is available at the output after a delay of t oe from the falling edge of g , assuming that e has been low and the addresses have been stable for at least t avqv -t glqv . standby mode the m27w202 has a standby mode which reduc- es the supply current from 15ma to 15a with low voltage operation v cc a 3.6v, see read mode dc characteristics table for details. the m27w202 is placed in the standby mode by applying a ttl high signal to the e input. when in the standby mode, the outputs are in a high imped- ance state, independent of the g input.
5/15 m27w202 table 7. read mode dc characteristics (1) (t a = C40 to 85 c; v cc = 2.7v to 3.6v; v pp = v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. maximum dc voltage on output is v cc +0.5v. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 10 a i lo output leakage current 0v v out v cc 10 a i cc supply current e = v il , g = v il , i out = 0ma, f = 5mhz v cc 3.6 v 20 ma i cc1 supply current (standby) ttl e = v ih 1ma i cc2 supply current (standby) cmos e > v cc C 0.2v v cc 3.6 v 15 a i pp program current v pp = v cc 10 a v il input low voltage C0.6 0.2 v cc v v ih (2) input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = C400a 2.4 v two line output control because otp eproms are usually used in larger memory arrays, this product features a 2 line con- trol function which accommodates the use of mul- tiple memory connection. the two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. for the most efficient use of these two control lines, e should be decoded and used as the prima- ry device selecting function, while g should be made a common connection to all devices in the array and connected to the read line from the system control bus. this ensures that all deselect- ed memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. system considerations the power switching characteristics of advanced cmos eproms require careful decoupling of the devices. the supply current, i cc , has three seg- ments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of e . the magnitude of transient current peaks is dependent on the ca- pacitive and inductive loading of the device at the output. the associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. it is recommended that a 0.1f ceram- ic capacitor be used on every device between v cc and v ss . this should be a high frequency capaci- tor of low inherent inductance and should be placed as close to the device as possible. in addi- tion, a 4.7f bulk electrolytic capacitor should be used between v cc and v ss for every eight devic- es. the bulk capacitor should be located near the power supply connection point.the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of pcb traces.
m27w202 6/15 table 8. read mode ac characteristics (1) (t a = C40 to 85 c; v cc = 2.7v to 3.6v; v pp = v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. 3. speed obtained with high speed ac measurement conditions. symbol alt parameter test condition m27w202 unit -100 (3) -120 (-150/-200) v cc = 3.0v to 3.6v v cc = 2.7v to 3.6v v cc = 2.7v to 3.6v min max min max min max t av qv t acc address valid to output valid e = v il , g = v il 80 100 120 ns t elqv t ce chip enable low to output valid g = v il 80 100 120 ns t glqv t oe output enable low to output valid e = v il 50 60 70 ns t ehqz (2) t df chip enable high to output hi-z g = v il 050060070ns t ghqz (2) t df output enable high to output hi-z e = v il 050060070ns t axqx t oh address transition to output transition e = v il , g = v il 000ns figure 5. read mode ac waveforms ai01818b taxqx tehqz a0-a16 e g q0-q15 tavqv tghqz tglqv telqv valid hi-z valid
7/15 m27w202 table 9. programming mode dc characteristics (1) (t a = 25 c; v cc = 6.25v 0.25v; v pp = 12.75v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . table 10. programming mode ac characteristics (1) (t a = 25 c; v cc = 6.25v 0.25v; v pp = 12.75v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. symbol parameter test condition min max unit i li input leakage current 0 v in v ih 10 a i cc supply current 50 ma i pp program current e = v il 50 ma v il input low voltage C0.3 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = C400a 2.4 v v id a9 voltage 11.5 12.5 v symbol alt parameter min max unit t avpl t as address valid to program low 2 s t qvpl t ds input valid to program low 2 s t vphpl t vps v pp high to program low 2s t vchpl t vcs v cc high to program low 2s t elpl t ces chip enable low to program low 2 s t plph t pw program pulse width 95 105 s t phqx t dh program high to input transition 2 s t qxgl t oes input transition to output enable low 2 s t glqv t oe output enable low to output valid 100 ns t ghqz (2) t dfp output enable high to output hi-z 0 130 ns t ghax t ah output enable high to address transition 0 ns programming when delivered, all bits of the m27w202 are in the '1' state. data is introduced by selectively pro- gramming '0's into the desired bit locations. al- though only '0's will be programmed, both '1's and '0's can be present in the data word. the m27w202 is in the programming mode when v pp input is at 12.75v, e is at v il and p is pulsed to v il . the data to be programmed is applied to 16 bits in parallel, to the data output pins. the levels re- quired for the address and data inputs are ttl. v cc is specified to be 6.25v 0.25v.
m27w202 8/15 figure 6. programming and verify modes ac waveforms tavpl valid ai00706 a0-a15 q0-q15 v pp v cc p g data in data out e tqvpl tvphpl tvchpl tphqx tplph tglqv tqxgl telpl tghqz tghax program verify figure 7. programming flowchart ai02734 n = 0 last addr verify p = 100 m s pulse ++n = 25 ++ addr v cc = 6.25v, v pp = 12.75v fail check all words 1st: v cc = 5v 2nd: v cc = 2.7v yes no yes no yes no presto ii programming algorithm presto ii programming algorithm allows pro- gramming of the whole array with a guaranteed margin, in a typical time of 13 seconds. program- ming with presto ii consists of applying a se- quence of 100 s program pulses to each word until a correct verify occurs (see figure 7). during programming and verify operation, a margin mode circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. no overprogram pulse is applied since the verify in margin mode at v cc much higher than 3.6v, provides necessary margin to each programmed cell. program inhibit programming of multiple m27w202s in parallel with different data is also easily accomplished. ex- cept for e , all like inputs including g of the parallel m27w202 may be common. a ttl low level pulse applied to a m27w202's p input, with e low and v pp at 12.75v, will program that m27w202. a high level e input inhibits the other m27w202s from be- ing programmed. program verify a verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. the verify is accomplished with e and g at v il , p at v ih , v pp at 12.75v and v cc at 6.25v.
9/15 m27w202 on-board programming the m27w202 can be directly programmed in the application circuit. see the relevant application note an620. electronic signature the electronic signature (es) mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. the es mode is functional in the 25c 5c am- bient temperature range that is required when pro- gramming the m27w202. to activate the es mode, the programming equipment must force 11.5v to 12.5v on address line a9 of the m27w202 with v pp = v cc = 5v. two identifier bytes may then be sequenced from the device out- puts by toggling address line a0 from v il to v ih . all other address lines must be held at v il during electronic signature mode. byte 0 (a0 = v il ) rep- resents the manufacturer code and byte 1 (a0 = v ih ) the device identifier code. for the stmicroelectronics m27w202, these two identifier bytes are given in table 4 and can be read-out on outputs q7 to q0. erasure operation (applies to uv eprom) the erasure characteristics of the m27w201 are such that erasure begins when the cells are ex- posed to light with wavelengths shorter than ap- proximately 4000 ?. it should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 ? range. data shows that constant exposure to room level fluo- rescent lighting could erase a typical m27w201 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. if the m27w201 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the m27w201 window to prevent unintentional erasure. the recommended erasure procedure for the m27w201 is exposure to short wave ultraviolet light which has wavelength of 2537 ?. the inte- grated dose (i.e. uv intensity x exposure time) for erasure should be a minimum of 15 w-sec/cm 2 . the erasure time with this dosage is approximate- ly 15 to 20 minutes using an ultraviolet lamp with 12000 w/cm 2 power rating. the m27w201 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. some lamps have a filter on their tubes which should be removed before erasure.
m27w202 10/15 table 11. ordering information scheme note: 1. high speed, see ac characteristics section for further information. 2. this speed also guarantees 80ns access time at v cc = 3.0v to 3.6v. 3. these speeds are replaced by the 120ns. 4. packages option available on request. please contact stmicroelectronics local sales office. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m27w202 -100 k 6 tr device type m27 supply voltage w = 2.7v to 3.6v device function 202 = 2 mbit (128kb x16) speed -100 (1,2) = 100ns -120= 120ns not for new design (3) -150 = 150 ns -200 = 200 ns package f = fdip40w (4) b = pdip40 k = plcc44 n = tsop40: 10 x 14 mm (4) temperature range 6 = C40 to 85 c options tr = tape & reel packing table 12. revision history date revision details november 1998 first issue 04/19/00 from product preview to data sheet fdip40w package added i cc2 stanbdy current changed
11/15 m27w202 table 13. fdip40w - 40 lead ceramic frit-seal dip with window, package mechanical data symbol mm inches typ min max typ min max a 5.72 0.225 a1 0.51 1.40 0.020 0.055 a2 3.91 4.57 0.154 0.180 a3 3.89 4.50 0.153 0.177 b 0.41 0.56 0.016 0.022 b1 1.45 C C 0.057 C C c 0.23 0.30 0.009 0.012 d 51.79 52.60 2.039 2.071 d2 48.26 C C 1.900 C C e 15.24 C C 0.600 C C e1 13.06 13.36 0.514 0.526 e 2.54 C C 0.100 C C ea 14.99 C C 0.590 C C eb 16.18 18.03 0.637 0.710 l 3.18 4.10 0.125 0.161 s 1.52 2.49 0.060 0.098 ? 8.13 C C 0.320 C C a 4 11 4 11 n40 40 figure 8. fdip40w - 40 lead ceramic frit-seal dip with window, package outline drawing is not to scale. fdipw-a a3 a1 a l b1 b e d s e1 e n 1 c a ea d2 ? eb a2
m27w202 12/15 table 14. pdip40 - 40 pin plastic dip, 600 mils width, package mechanical data symbol mm inches typ min max typ min max a4.45 C C 0.175 C C a1 0.64 0.38 C 0.025 0.015 C a2 3.56 3.91 0.140 0.154 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 51.78 52.58 2.039 2.070 d2 48.26 C C 1.900 C C e 14.80 16.26 0.583 0.640 e1 13.46 13.99 0.530 0.551 e1 2.54 C C 0.100 C C ea 15.24 C C 0.600 C eb 15.24 17.78 0.600 0.700 l 3.05 3.81 0.120 0.150 s 1.52 2.29 0.060 0.090 a 0 15 0 15 n40 40 figure 9. pdip40 - 40 lead plastic dip, 600 mils width, package outline drawing is not to scale. pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2
13/15 m27w202 table 15. plcc44 - 44 lead plastic leaded chip carrier, package mechanical data symbol mm inches typ min max typ min max a 4.20 4.70 0.165 0.185 a1 2.29 3.04 0.090 0.120 a2 C 0.51 C 0.020 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 17.40 17.65 0.685 0.695 d1 16.51 16.66 0.650 0.656 d2 14.99 16.00 0.590 0.630 e 17.40 17.65 0.685 0.695 e1 16.51 16.66 0.650 0.656 e2 14.99 16.00 0.590 0.630 e 1.27 C C 0.050 C C f 0.00 0.25 0.000 0.010 r 0.89 C C 0.035 C C n44 44 cp 0.10 0.004 figure 10. plcc44 - 44 lead plastic leaded chip carrier, package outline drawing is not to scale. plcc d ne e1 e 1 n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2
m27w202 14/15 table 16. tsop40 - 40 lead plastic thin small outline, 10 x 14 mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 13.80 14.20 0.5433 0.5591 d1 12.30 12.50 0.4843 0.4921 e 9.90 10.10 0.3898 0.3976 e0.50 C C 0.0197 C C l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n40 40 cp 0.10 0.0039 figure 11. tsop40 - 40 lead plastic thin small outline, 10 x 14 mm, package outline drawing is not to scale. tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
15/15 m27w202 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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